Delay Metric for On-chip Rlcg Coupled Interconnects for Ramp Input
نویسندگان
چکیده
In this paper we have put forward an analytical model which can could accurately compute the on chip interconnect delay using distributed RLCG segments. With the increasing level of on chip integration the interconnect delay has acquired prominence for performance driven layout synthesis. Also in higher frequency range of the order of GHz , the effect of shunt conductance and inductance cannot be ignored. Our proposed analytical model is based on II and III central moment of the interconnect transfer function .We have taken the ramp as input signal as for RLCG interconnection Elmore Delay can deviate up to 100% or more than the spice computed delay since it is independent of rise time. Experimental results show that the estimated delay using our first few central moments based model performed for 0.18μm technology 5% of SPICEcomputed delay across a wide range of interconnect parameter values.
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